Senior Engineer

Tellabs (www.tellabs.com) designs, manufactures, markets and services data, voice/ video transport, switching/routing, network access systems/ voice-quality enhancement solutions. The company's products are used worldwide by the providers of communications services. Tellabs (www.tellabs.com) helps the world's leading communications service providers build tomorrow's converged networks of voice, data and video. We design, build and service optical networking, broadband access and voice-quality enhancement equipment. In fact, most telephone calls and Internet sessions in the United States flow through equipment from Tellabs.



POSITION OVERVIEW:

Seeking engineers with at least 7 years of high speed ASIC design experience. This position involves specifying, designing, verifying, synthesizing, performing static timing analysis and floorplanning at block level as well as chip level. The ideal candidate must have:
* Knowledge and experience with writing technical specifications, Verilog coding, synthesis, verification, static timing analysis, floorplanning and post silicon debugging.
* Designed for at least one 1M gates or larger ASIC using 0.13 um or smaller technology and running at 200 MHz or more as well as done some verification work for that ASIC.
* Experience in the Networking industry.
* Effective communication skills and a strong teamwork approach.
* The flexibility and desire to work in a fast-paced environment.




QUALIFICATIONS:

7 years design experience of high speed ASICs (must have designed for at least one 1M gates or larger ASIC using 0.13 um or smaller technology and running at 200 MHz or more as well as done some verification work for that ASIC).



YEARS OF EXPERIENCE: 7 years

EDUCATION: Bachelors Degree

TRAVEL PERCENTAGE: 0

SHIFT: 1st Shift


Tellabs is an Equal Opportunity Employer M/F/D/V. Qualified minorities, women, individuals with disabilities and veterans are strongly encouraged to apply.