Sr. Physical Design Engineer

Visualize your future . . . We DoNVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees our shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold. SR. PHYSICAL DESIGN ENGINEER #746876

Responsibilities:Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets. Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure, - Static timing analysis, power and noise analysis and back-end verification across multiple projects. Minimum Requirements:BSEE or BSCS 7+ years of experience in large VLSI physical design implementation on 0.15u, 0.13u, or 90 nanometer technology. Successful track record of delivering products to production is a must. Understanding of custom Macro blocks such as RAMs, CAMs, high-speed IO drivers. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues. Working knowledge of deep sub-micron routing issues as they relate to power and timing. Circuit level comprehension of time critical paths. Spice experience a plus. Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma. Proficiency using Perl, TCL, Scheme, Make scripting is preferred.EOE

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