VLSI Design Engineer

JOB SUMMARY:

As a Senior VLSI Design Engineer you will work closely with our System Engineers to understand the functional requirements of our products.  You will be responsible for developing chip architectures and implementing those architectures in RTL using System Verilog. You will use unit level test environments for verification/debug and drive your design through synthesis and timing closure.  You will work with state of the art technologies such as TSMC 90nm and 0.13um CMOS using our in-house COT flow.

 

JOB QUALIFICATIONS:

The candidate must have a solid background in all aspects of complex IC design including architecture, RTL, simulation, debug, synthesis and timing. Experience with Ethernet related devices is a plus, along with any of the following interfaces and functions: SPI-4.2, 10G Ethernet (XAUI), 1G Ethernet (SGMII), Ethernet MAC operations, SDRAM interfaces (DDR), and IP traffic management. Prior experience with assertion based verification methodologies will be an advantage.

The candidate must have 6-10 years of experience in chip architecture/design and a proven track record of developing very complex IC's (5 million gate+) that are sold into the telecomm and datacomm markets. Experience in high speed digital circuit design greater than 400MHz is a plus. Should be familiar with signal integrity issues, modeling and analysis of high speed circuits such as LVDS, DDR and SERDES.

EDUCATIONAL REQUIREMENTS: BSEE minimum requirement

 

Contact: John Visconti at 978-667-6680 or mailto:jv@cae-jobs.com.  Career Counseling professional specializing in Design Automation for more than 20 years.  Qualified EDA  professionals should feel free to call or e-mail at any time with any career related questions.  All inquiries are held in the strictest confidence.