ASIC Engineer, Sr. - Bedminster NJ

Role Will be involved in design and verification of next generation OFDM baseband modem SoC. Responsibilities will include block level functional specifications, RTL logic design, block level synthesis and formal verification, functional verification through simulation and fpga emulation. Also responsible for writing block-level design specifications, functional test plans, programming reference and constraint guidelines where appropriate. May need to get involved with ASIC vendor during backend flow to achieve timing closure or address issues requiring ecos.

Skills/Experience
Strong skills in RTL logic design (VHDL or Verilog) and verification. Experience in ASIC design flow including block-level synthesis, formal verification and static timing analysis. Experience with functional verification utilizing high level methodologies and FPGA emulation platforms. Must have familiarity with the design of wireless interfaces and digital signal processing algorithms. Demonstrable experience in designing IEEE and/or telecom standards-based modules is highly advantageous. Effective communications skills are essential.

Additional Skills
Experience with static timing analysis using Synopsys Primetime and familiarity with DFT and backend ASIC flow and tools a plus. Experience with RTL design verification using ModelSim a plus.

Education Requirements
Bachelor's/Master's in Electrical Engineering preferred with five to ten plus years applicable experience.

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