ASIC / FPGA Engineer - Senior

This position reports to the ASIC/FPGA Technical Manager and provides definition, design, verification and documentation for Application Specific Integrated Circuit (ASIC) development and Field Programmable Gate Array (FPGA) development. This individual is responsible for architecture, design, implementation and verification of logic.

This position requires the implementing and/or coordinating of all aspects of the process flow from definition, high level design to synthesis, place and route, and timing and power use. This individual may be involved in defining and reviewing vendor capability, CAD flows, vendor libraries and processes, specifying of custom analog blocks, floor planning, timing, chip assembly, layout, design checking, design for test, design for manufacturability, foundry interfacing, test and production ramp-up.

The Senior ASIC/FPGA engineer is responsible for developing automated ASIC and FPGA verification strategies using Verilog and high level verification tools (e.g. Testbuilder, System C, etc).

***And other duties as assigned or needed.***

Experience and Skills:
This position requires 6+ years of experience in ASIC / FPGA development and verification and a BSEE, or equivalent combination of education and additional experience in this discipline. The candidate will have the following additional qualifications:

? Experience in developing product requirements specifications and design documents
? A demonstrated proficiency in writing functional requirements and documenting designs
? Working among various engineering disciplines including hardware, firmware, software, system test and manufacturing
? Mentorship of ASIC/FPGA engineers and the ability to lead/assist in solving technical issues
? Demonstrated knowledge in ASIC/FPGA lifecycles
? Experience with logic analyzers, scopes and other debug tools
? Proven ability to deliver complex commercial ASIC/FPGA products
? A proven ability to manage multiple tasks concurrently
? Experience with Verilog HDL and high level verification strategies/tools
? Expertise in design for testability and manufacturability
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