ASIC Verification Engineer, Senior Staff

Role Lead development of verification environment and execute system-level verification plan for next generation wireless baseband modem SoC. Environment will verify all stages of development including RTL design, FPGA emulation, software co-verification, and gate level simulation. Verification platform will utilize industry-standard high level verification language methodologies and be capable of leveraging existing verification IP written in C/C++.

Skills/Experience
Must have strong skills in HDL coding (VHDL, Verilog), C/C++, and scripting (Perl, Python, UNIX shell). Experience with SoC verification methodologies including a working knowledge of high level verification languages (SystemC, Vera) and tools (ModelSim or similar) is also required. Must be able to lead a small team working in a fast-paced, dynamic environment.

Additional Skills
Experience in FPGA implementation or emulation is desired. Familiarity with system-level SoC/ASIC (ESL) design/verification tool suites beneficial.

Education Requirements
Bachelor's/Master's in Electrical Engineering preferred with Ten to Fifteen plus years related experience.

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