Design Verification Engineer - All Levels

Role As a Verification Engineer, you will be responsible for understanding the expected functionality of designs, developing corresponding testplans, designing and developing our verification environment components, and applying these to verify complex designs until coverage goals are achieved, and completing all required verification activities to insure high quality commercial success of our products. Design we verify include multi-media, modem, bus, DMA, various peripherals, security, memory controller, RISC/DSP processors. As verification is a rapidly changing field and consumes majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis.

Skills/Experience
Experience with verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs is a plus. RTL design experience and/or very strong OO programming experience is also a plus. Knowledge of wireless/wired communications and protocols or graphics/video multi-media a plus. Good written and oral communications skills required.

All levels - seeking engineers with a range of verification experience.

* Solid OOPs programming skills

* Strong verification skills: test planning, problem solving, debug, adversarial testing

* Strong working knowledge of HVLs: VERA/e-Specman

* Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting

Additional Skills

Education Requirements
BS/MS/PhD in Electrical Engineering or Computer Science

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