EDA/CAD Engineer (multiple openings)

EDA/CAD Engineer (3 openings) +++++  EDA/CAD Engineer - Cadence tool support engineer  +++++You will help maintain and support PDK?s.  Candidates should be familiar with creating component symbols, schematics, CDF's, P-Cells and Skill callback functions.  The successful candidate will also work closely with design teams to provide tool support and to improve the design methodology. Requirements/Qualifications:Bachelor's or Master?s in CS or EEMust have 2+ years industry experience (preferably in an analog environment.)Must have a strong UNIX and programming (C, PERL, Skill) background.Experience developing Process Design Kits (PDKs) a plus. +++++  EDA/CAD Engineer - ASIC library development  +++++ We are seeking a CAD Engineer with experience in developing ASIC libraries and behavior models.  The successful candidate should be familiar with circuit design and simulation, cell view creation (schematic, symbol, layout, etc.), behavior modeling, and analog/digital design flows.  The responsibilities include ASIC library (standard cell and I/O) development and behavior modeling (SABER, Verilog, Verilog-A/AMS, etc.). Requirements/Qualifications:Bachelor or Master's Degree in EE, CS or CE is required. Familiar with analog and logic circuits. Experience with behavior language modeling. Familiar with SABER is a plus. Experience with analog and digital simulation tools. Strong Unix and programming (PERL, C) background. SKILL programming is a plus. +++++  EDA/CAD Engineer - Synthesis flows and methodologies  +++++ We are seeking an energetic CAD Engineer with a strong background in ASIC synthesis tools and flows.  Responsibilities include but not limit to new release QA, installation, setup, interfacing with vendors, supporting design community, implementing and documenting design flow and methodologies, etc.  The successful candidate will also work closely with design teams to provide tool support and to improve the design methodologies such as constraint generation, timing closure, DFT compliance, low power optimization, etc. Requirements/Qualifications:Bachelor's or Master's degree in CS or EE is required. Must have 5 years experience in synthesis, timing closure. Must have a strong Unix/Linux background. Experienced with Design Compiler, PrimeTime, PowerCompiler, DFT Compiler. Strong background in timing closure flow. Familiar with Verilog, VHDL and/or SystemVerilog. Strong interpersonal, communication and analytical skills Strong background in DFT or design verification is a plus. Interested and qualified candidates please email your resume to:Javier Leon jleon@alchemytechnical.com http://www.alchemytechnical.com/ Do you know anyone who would appreciate knowing about this job?Please forward this message to them.