Elect Design Engineer Sr Staff

Job Description:    

Sr Staff logic designer focused on products for use in mobile handset devices. Responsible for micro-architecture, logic design, synthesis, and timing closure for chips that combine complex logic and customs structures.

 

Job Specific Requirements:      

Must have a track record of successful products with major logic design contributions to the success of those products. Must be familiar with logic design in custom and place and route environments. Must be familar with Verilog HDL and synopsys synthesis flows. Familiarity with design verificaion and verification flows, including Vera and formal verification, are a plus.

 

Minimum Education & Work Experience:    

BS EE/CS or equivalent. MS/PHd desired. Minimum 5 years experience.

 

EOE