Hardware Design Staff Engineer/ASIC & RTL verification

Hardware Design Staff Engineer  

 

JOB Description

?  This Sr ASIC Design Engineering position is located at the STMicroelectronics site in Longmont, CO.

?  The essential function is the specification, design and integration of I/O buffers and interfaces for data storage SoC designs in cooperation with multiple in-house and external IP providers.

?  Design validation through RTL, gate-level timing simulation and static timing analysis.  Interface with customer, IP providers and operations in the US,  Europe and Asia.

 

 

JOB Requirements:

?  A BS degree in Computer Science or Electrical Engineering is required?

?  A minimum 5 years of ASIC Design experience.

?  Required skills include proven track record in VHDL or Verilog RTL design, Design Compiler and Prime Time hands-on experience. 

?  Strong communication skills required.

?  Understanding of the ASIC design flow and IO buffer design is preferred.

?  Familiarity with DFT and physical design is a plus.

 

ADDITIONAL Desirable Skills

?  Experience with ASIC, SoC and Super Integration

?  Experience with PrimeTime, PrimrPower, PowerCompiler, and PhysicalCompiler, DesinCompiler, TestCompiler and Timing closure.

?  DFT, STA ARM DRAM IO, DDR SATA, MMC, CE-ATA ESD, TCL and DFT

 

About STMicroelectronics

STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2004, the Company's net revenues were $8.76 billion and net earnings were $601 million. Further information on ST can be found at www.st.com.