Physical Verification Engineer

National Semiconductor, the industry's premier analog company, creates high performance analog devices and subsystems.  National's leading-edge products include power management circuits, display drivers, audio and operational amplifiers, communication interface products and data conversion solutions. National's key analog markets include wireless handsets, displays and a variety of broad electronics markets, including medical, automotive, industrial, and test and measurement applications. Headquartered in Santa Clara, California, National reported sales of $2.16 billion for its most recent fiscal year.

 

Our Library Technologies group is looking for a MTS level Physical Verification Engineer.  The engineer will develop and support physical verification runsets in CMOS, BiCMOS and Biploar process technologies. The successful candidate must be familiar with physical verification development methodology and related tools such as Diva, Dracula, Hercules, and Assura. The runsets include DRC, LVS, ERC, Softcheck, Antenna, and RCX (parasitic post-layout analysis). The candidate should have broad technical skill in Analog and mixed-signal design flows.  It is required that the candidate possess good communication skills and be a good team player as this position will lead major projects and work with cross-functional teams.

 

Requirements:

MSEE degree with 5 - 10 years of industrial experience.  Cadence Framework, SKILL programming language (Cadence propriety programming language for coding DRC/LVS, ..).

 

As an Equal Opportunity Employer, National Semiconductor encourages and supports a diverse workplace.