Sr. Packaging Design Engineer

Job Description

 Perform layout of all ceramic and organic substrates used to package Silicon Laboratories' mixed-signal IC products. Work with IC designers on new die designs to optimize die-pad/bump placement for maximum electrical performance and minimum package cost.Generate and maintain package netlists.Interface with substrate suppliers to understand process groundrules and to select the best technologies available. Communicate supplier groundrule and process capabilities to SiLabs design and marketing teams to assist in the selection of packaging on new programs.Translate designs from Cadence APD to formats required to communicate with suppliers and internal chip designers.Coordinate transfer (tape-out) of package designs to substrate and assembly suppliers.Generate Bond Diagrams and Assembly Documentation for all Silicon Laboratories? products.Generate Package Outline drawings to support Product Datasheets. Send resume to: jobs_design@silabs.com

 

 

 Requirements

 BSME/BSEE with 5+ years experience in semiconductor package design.Must be proficient in Cadence APD and have experience designing complex flip-chip and multi-chip module (MCM) packages.Should be familiar with ceramic and organic (build-up) substrate groundrules and processes.Must be proficient in the use of AutoCAD to generate 2-D drawings. Must have good understanding of Geometric Dimensioning and Tolerancing. Needs to work well as part of a cross-functional team.