Staff Engineer - Digital ASIC/FPGA Design (04039)

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ITT Aerospace/Communications (A/CD), Ft. Wayne, Indiana.

Lead the top level architecture design of ASICs/FPGAs as well as the design of ASICs/FPGAs and interface with System Engineering during the system design phase for trade-offs. Perform design and verification of ASICs/FPGAs for communication systems. Review designs for requirement compliance, robustness, and adherence to guidelines and standards. Help develop and implement improvements to the design process for cycle time reduction and robustness.

Equivalent Educational Requirements: BS (MS or PhD preferred) in Electrical Engineering.

Experience Required - A minimum of eight years engineering experience using VHDL to design FPGA/CPLDs with preferred signal processing and Digital/CCA Design. Experience with timing constraints and static timing analysis, behavioral VHDL modeling, DSP/GPP emulators, design verification and leveraging system algorithm modeling to verity VHDL models.

Successful candidate will be a demonstrated self-starter and team player. Demonstrated success in developing complex devices from concept through implementation required.

Knowledge Required - Advanced and comprehensive knowledge in the area of digital/ASIC/FPGA design.

Candidate selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. U.S. citizenship required.

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