Staff/Principal Physical Design Engineer

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Staff / Principal Physical Design Engineer

Req#: 2605

 

Primary Job Responsibilities:

Carry out CMOS digital circuit physical implementation using your engineering skills, CAD software, scripts, and existing design flows as team leader or as a key contributor.  Be responsible for all aspects of chip physical implementation from RTL to GDSII including floor plan, timing closure, noise closure, power grid integrity, and LVS/DRC.  Develop implementation plans and schedules. Create and maintain re-usable scripts.  Invent, develop, and maintain important complex scripts used by others on the team.  Guide, mentor, and instruct others toward efficient completion of projects.  Contribute to methodology development, design kit quality, and ?bring-up? of new technologies by defining, implementing, and debugging new procedures; identifying, debugging, and solving problems; and defining and running tests on existing scripts and procedures.  Will also take on and supervise tasks that reach outside of primary area of expertise.

 

Products are from one or more of the following: Embedded Power PC processors, network processors, framers, PHY layer chips, and storage chips. The technology is 130nm and 90nm CMOS; chip sizes range from 3mm to 16mm per side; clock rates range from 125MHz to 2.5GHz.

 

Our team works designs from netlist to tape out using CAD tools such as Magma, StarRCXT, PrimeTime SI, and Calibre.  Scripting is Tcl and Perl.  Other tools may be inserted in the flow as needed.  Throughout the process, a high value is placed on design quality, repeatability of successful techniques, and depth of implementation checking.

 

 

Education Requirement or Equivalent:

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Physics or equivalent work experience.

 

 

Experience Requirement:

BS: 6 years; MS: 4 years; PhD: 2 years; or equivalent work experience in the field of CMOS physical implementation or the related fields of synthesis, simulation, design automation, reverse engineering, or chip level internal diagnostics or failure analysis.  Must have completed layouts on 3 or more chips that have been built in silicon and work.  Must have resolved non-routine design issues or problems.  Must have contributed methodology solutions and scripting to design flows used by others.

 

 

Special Skills or Knowledge Required:

Required skills are in-depth understanding of the principles of CMOS design and digital logic circuitry, and proficiency at programming in Tcl, Perl, or C in the UNIX/Linux environment.

 

It is required to have expert level skill using 3 or more, and some knowledge of how to configure 1 or more of the following tools: Magma, Astro, ChipBench, Physical Compiler, SoC Encounter, RedHawk, PrimeTime, EinsTimer, Design Compiler, StarRCXT, Calibre, Hercules, Diva, or similar tools.