Verification Engineer

Verification Engineer Description: Exciting opportunity to work with a very bright group of folks in Silicon Valley, CA on ASIC designs doing verification!!
Fastest chips, amazing product and a great group of folks. Solid company but feels like a start up (people that work there say that).
You will be working on integrated projects; developing stand-alone and full-chip test env, support for verification of IP integration, and implementing the test cases and verification models. You will also
develop and maintain stand-alone and full-chip test environment for IP integration, create and maintain simulation models for peripheral interfaces/devices and write test cases in C/C++/Verilog




Requirements:
1. MSEE 5+ years experiences
2. Debugging- Strong problem solving capability with waveform debug tools (Required)
3. Test case programming- Familiar with Perl/Make scripting, C/C++ or Verilog (Required)
4. Preferred industry experience- PC system, peripheral I/O interface (such USB, IDE, SATA, PCIE and PCI)
5. ASIC verification methodologies- Knowledge of assertion, coverage measurement and random vector generation
MUST APPLY BY EMAILING